Scalable Test Pattern Generator Design Method for BIST

A scalable built-in self-test (BIST) equipment design method for combinational or full-scan circuits based on a design of a test pattern generator producing vectors detecting 100% of stuck-at faults is proposed in this paper. Basic principles of the proposed BIST design method are similar to well-known and commonly used methods like bit-fixing, bit-flipping, etc. We introduce a new TPG design algorithm, which offers a good scalability, in terms of the test time, BIST area overhead and the BIST design time. The basis of the test pattern generator is a combinational block the Decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by an ATPG tool. The Column-Matching algorithm to design the decoder is proposed. Maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns.